Over a period of time use of memory devices in electronic systems has increased significantly. The memory devices form key components in most of electronic designs. The memory devices, for example, Dynamic Random Access Memory (DRAM) devices, are popular due to their low cost and high volume use. The low cost results from simple and regular structure of the DRAM devices which is easy to manufacture. The memory devices and access to the memory devices are controlled using memory controllers. The memory controllers may be interfaced with the memory devices. The memory controllers provide an access mechanism and implement various timing and control functions for the memory devices. The memory controllers are also offered as pre-designed Intellectual Property (IP) blocks. The more efficient an IP block is the more useful it is. The memory devices require several advanced features to achieve performance levels required by the electronic systems. The advanced features put additional requirements on the memory controllers and make it more difficult for a designer to create the memory controllers. Therefore, an efficient memory controller is required.
In order to increase processing speed of the electronic systems it is necessary to improve access time to the memory devices which in turn puts an additional requirement on the memory controllers. In a conventional memory controller implementation for a memory device an attempt to improve access time is made by taking a stream of access requests and optimizing the access requests to make sure that no access requests to the memory device are wasted. For example, addresses to a same section, such as a row, of a bank of the memory device can be made more quickly than accesses to any other row in the bank. However, only a few (usually just 2 or 3 accesses) optimizations can be made in such memory controller implementation due to the limitation to the length of the stream of the access requests. Further, the memory controller implementation makes use of a traditional state machine to make access priority decisions and the traditional state machine becomes unmanageably complex as multiple accesses are added to a decision mechanism. Hence, an efficient memory controller implementation is desired. Further, read-modify-write operations associated with the DRAM must also be handled.
In order to maximize performance in the electronic systems, it is important for the memory device and memory controller to provide both minimum latency and maximum memory bandwidth. Hence, a memory controller implementation that minimizes latency and maximizes bandwidth is desired.